IAR EWAVR interrupt vectors from iom128.h

Address Labels Code Comment

$0000 jmp RESET ; Reset Handler

$0002 jmp EXT_INT0 ; IRQ0 Handler

$0004 jmp EXT_INT1 ; IRQ1 Handler

$0006 jmp EXT_INT2 ; IRQ2 Handler

$0008 jmp EXT_INT3 ; IRQ3 Handler

$000A jmp EXT_INT4 ; IRQ4 Handler

$000C jmp EXT_INT5 ; IRQ5 Handler

$000E jmp EXT_INT6 ; IRQ6 Handler

$0010 jmp EXT_INT7 ; IRQ7 Handler

$0012 jmp TIM2_COMP ; Timer2 Compare Handler

$0014 jmp TIM2_OVF ; Timer2 Overflow Handler

$0016 jmp TIM1_CAPT ; Timer1 Capture Handler

$0018 jmp TIM1_COMPA ; Timer1 CompareA Handler

$001A jmp TIM1_COMPB ; Timer1 CompareB Handler

$001C jmp TIM1_OVF ; Timer1 Overflow Handler

$001E jmp TIM0_COMP ; Timer0 Compare Handler

$0020 jmp TIM0_OVF ; Timer0 Overflow Handler

$0022 jmp SPI_STC ; SPI Transfer Complete Handler

$0024 jmp USART0_RXC ; USART0 RX Complete Handler

$0026 jmp USART0_DRE ; USART0, UDR Empty Handler

$0028 jmp USART0_TXC ; USART0 TX Complete Handler

$002A jmp ADC ; ADC Conversion Complete Handler

$002C jmp EE_RDY ; EEPROM Ready Handler

$002E jmp ANA_COMP ; Analog Comparator Handler

$0030 jmp TIM1_COMPC ; Timer1 CompareC Handler

$0032 jmp TIM3_CAPT ; Timer3 Capture Handler

$0034 jmp TIM3_COMPA ; Timer3 CompareA Handler

$0036 jmp TIM3_COMPB ; Timer3 CompareB Handler

$0038 jmp TIM3_COMPC ; Timer3 CompareC Handler

$003A jmp TIM3_OVF ; Timer3 Overflow Handler

$003C jmp USART1_RXC ; USART1 RX Complete Handler

$003E jmp USART1_DRE ; USART1, UDR Empty Handler

$0040 jmp USART1_TXC ; USART1 TX Complete Handler

$0042 jmp TWI ; Two-wire Serial Interface Interrupt handler

$0044 jmp SPM_RDY ; SPM Ready Handler

$0046 RESET: ldir16, high(RAMEND) ; Main program start

$0047 out SPH, r16 ; Set stack pointer to top of RAM

$0048 ldi r16, low(RMAEND)

$0049 out SPL, r16

$004A sei ; Enable interrupts

$004B <instr> xxx

/*==============================*/

/* Interrupt Vector Definitions */

/*==============================*/

/* NB! vectors are specified as byte addresses */

#define RESET_vect (0x00)

#define INT0_vect (0x04)

#define INT1_vect (0x08)

#define INT2_vect (0x0C)

#define INT3_vect (0x10)

#define INT4_vect (0x14)

#define INT5_vect (0x18)

#define INT6_vect (0x1C)

#define INT7_vect (0x20)

#define TIMER2_COMP_vect (0x24)

#define TIMER2_OVF_vect (0x28)

#define TIMER1_CAPT_vect (0x2C)

#define TIMER1_COMPA_vect (0x30)

#define TIMER1_COMPB_vect (0x34)

#define TIMER1_OVF_vect (0x38)

#define TIMER0_COMP_vect (0x3C)

#define TIMER0_OVF_vect (0x40)

#define SPI_STC_vect (0x44)

#define USART0_RXC_vect (0x48)

#define USART0_UDRE_vect (0x4C)

#define USART0_TXC_vect (0x50)

#define ADC_vect (0x54)

#define EE_RDY_vect (0x58)

#define ANA_COMP_vect (0x5C)

#define TIMER1_COMPC_vect (0x60)

#define TIMER3_CAPT_vect (0x64)

#define TIMER3_COMPA_vect (0x68)

#define TIMER3_COMPB_vect (0x6C)

#define TIMER3_COMPC_vect (0x70)

#define TIMER3_OVF_vect (0x74)

#define USART1_RXC_vect (0x78)

#define USART1_UDRE_vect (0x7C)

#define USART1_TXC_vect (0x80)

#define TWI_vect (0x84)

#define SPM_RDY_vect (0x88)

- from AtMega128 Datasheet